In this regard, what is the maximum delay generated by the 15 Mhz clock frequency in accordance to a mode 1 operation of the timer?
Maximum count of mode 1 is 65536, hence the maximum time delay that can be generated is 65536 * 1 microsec = 65536 microsec = 65.536 mili- sec.
Also, what is the operation for mode 1? Mode 1 IT operations are focused on legacy applications and systems that are typically found in an organization's on-premise data center.
Also asked, which timer register has both timers in it?
8051 has two timers Timer0 (T0) and Timer1 (T1), both are 16-bit wide. Since 8051 has 8-bit architecture, each of these is accessed by two separate 8-bit registers as shown in the figure below. These registers are used to load timer count.
Is this a valid statement Setb A *?
Explanation: SETB is used to set a bit of a register. A stands for accumulator which is an 8 bit register, so it is an invalid instruction.